Underlap Channel Nanoscale Dopant-Segregated Schottky Barrier SOI MOSFET for Low-Power Mixed Signal Circuits

In this paper, underlap channel dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been proposed, in which the increased effective channel length (Leff) due to underlap channel at both source/drain (S/D) sides reduces the leakage currents, short-channel effects and the parasitic capacitances as compared to overlap channel DSSB SOI MOSFET. Although in strong inversion the voltage drop across the underlap lengths at S/D reduces the drive current of the proposed device, in weak inversion defined at ID = 5 μA/μm at VDS = 0.5 V the analog figures of merit (FOM) of this device are improved. Further, the mixed-mode simulation results of CMOS inverter and the ring-oscillator circuits show that, at lower supply voltage (i.e.VDD = 0.5 V), both power dissipation (PD) and the delay in the case of proposed device are reduced as compared to overlap device. Thus, the improved analog FOM and reduced PD and the delay at lower supply voltage makes the proposed underlap device suitable for low-power mixed-signal circuits.